ADLINK Technology NuDAQ / NuIPC LPCI-7200S User's Guide

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NuDAQ
®
/ NuIPC
®
PCI-7200 / cPCI-7200 / LPCI-7200S
12MB/S High Speed
Digital Input/ Output Card
User’s Guide
Recycled Paper
Page view 0
1 2 3 4 5 6 ... 70 71

Summary of Contents

Page 1 - User’s Guide

NuDAQ®/ NuIPC® PCI-7200 / cPCI-7200 / LPCI-7200S 12MB/S High Speed Digital Input/ Output Card User’s Guide Recycled Paper

Page 2

2 • Introduction 1.2 Features The PCI-7200 high-speed DIO Card provides the following advanced features:  32 TTL digital input channels  32 TTL

Page 3

Introduction • 3 z Input Voltage: Low: Min. 0V; Max. 0.8V High: Min. +2.0V z Input Load: Low: +0.5V @ -0.6mA max. High: +2.7V @

Page 4 - Getting Service from ADLINK

4 • Introduction 1.4 Software Supporting ADLINK provides versatile software drivers and packages for users’ different approach to building a system.

Page 5 - Table of Contents

Introduction • 5 1.4.2 PCIS-LVIEW: LabVIEW® Driver PCIS-LVIEW contains VIs to interface with NI’s LabVIEW® software package. PCIS-LVIEW supports Wind

Page 6

6 • Introduction 1.4.7 PCIS-ISG: ISaGRAFTM driver The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG

Page 7 - How to Use This Guide

Installation • 7 2 Installation This chapter describes how to install the PCI-7200. Package contents and unpacking information are described. Becaus

Page 8

8 • Installation 2.2 Unpacking The PCI-7200 card contains sensitive electronic components that can be easily damaged by static electricity. The work

Page 9 - Introduction

Installation • 9 2.4 PCI-7200/cPCI-7200/LPCI-7200S’s Layout CN1PCI-7200 Rev A1CN2ALTERAPCI -BusController. .. .. .. .. .. .. .. ..

Page 10 - 1.3 Specifications

10 • Installation Figure 2.1(b) cPCI-7200 Layout Diagram

Page 11

Installation • 11 Figure 2.1(c) LPCI-7200S Layout Diagram CN1BCN1ADimension: mm

Page 13

12 • Installation Figure 2.1(d) LPCI-7200S with standard PCI bracket Layout Diagram Dimension: mm

Page 14 - 1.4.8 PCIS-ICL: InControl

Installation • 13 2.5 Hardware Installation Outline Hardware configuration These PCI cards (or CompactPCI, Low Profile PCI cards) are equipped with

Page 15 - Installation

14 • Installation 2.6 Connector Pin Assignments 2.6.1 PCI-7200 Pin Assignments The PCI-7200 comes equipped with one 37-pin D-Sub connector (CN2) loc

Page 16 - 2.2 Unpacking

Installation • 15 1234561011121314157891617181920 21 22 23 24 25 26 27 28 30 31 32 33 29 35 36 37 34 DI 1DI 2DI 3DI 4DI 5DI 6DI 7DI 8 DI10DO10DO11DO

Page 17 - Controller

16 • Installation 2.6.2 cPCI-7200 Pin Assignments (1)(2)(3)(52)(53)(51)(48)(49)(50)(98)(99)(100) Figure 2.4 CN Pin Assignments (1) DO0

Page 18

Installation • 17 2.6.3 LPCI-7200S Pin Assignments DIN0 A1 A35 GND DIN1 A2 A36 GND DIN2 A3 A37 GND DIN3 A4 A38 GND DIN4 A5 A39 GND DIN5 A6 A40

Page 19

18 • Installation DOUT0 B1 B35 GND DOUT1 B2 B36 GND DOUT2 B3 B37 GND DOUT3 B4 B38 GND DOUT4 B5 B39 GND DOUT5 B6 B40 GND DOUT6 B7 B41 GND DOUT7

Page 20

Installation • 19 2.7 8254 for Timer Pacer Generation Timer 0Timer 1Timer 2CLK0GATE0OUT0CLK1GATE1CLK2GATE2OUT1OUT28254 Timer/CounterDigital Input Ti

Page 21

20 • Installation 2.8 LPCI-7200S PCI Bus Signaling Low-Profile PCI is a new PCI card standard for space-constrained system designs. The new form fac

Page 22

Register Format • 21 3 Register Format 3.1 I/O Registers Format The PCI-7200 occupies 8 consecutive 32-bit I/O addresses in the PC I/O address space.

Page 23

©Copyright 2003 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 2.30: October 13, 2003 Part No: 50-11102-101 The information in this docume

Page 24

22 • Register Format 3.2 Digital Input Register (BASE + 10) 32 digital input channels can be read from this register Address: BASE + 10 Attribute: R

Page 25

Register Format • 23  Digital Input Mode Setting: I_ACK: Input ACK Enable 1: Input ACK is enabled (input ACK will be asserted after input data is re

Page 26 - Installation

24 • Register Format O_TRG: Digital Output Trigger Signal This bit is used to control the O_TRG output of PCI-7200; the signal is on CN1 pin 36 of PC

Page 27 - 4MHz Clock

Register Format • 25 T0_EN: Interrupt is triggered by timer 0 output. 1: Timer 0 interrupt is enabled 0: Timer 0 interrupt is disabled T1_EN: Interr

Page 28

26 • Register Format T1_T2: Timer 1 is cascaded with timer 2 1: Timer 1 and timer 2 are cascaded together; output of timer 2 connects to the clock in

Page 29 - Register Format

Register Format • 27 3.6 8254 Timer Registers (BASE + 0) The 8254 timer/counter IC occupies 4 I/O address. Users can refer to Tundra's or Intel

Page 31

Operation Theory • 29 4 Operation Theory In PCI-7200, there are four data transfer modes can be used for digital I/O access and control, these modes

Page 32 - Byte 7 6 5 4 3 2 1 0

30 • Operation Theory 4.2 Timer Pacer Mode The digital I/O access control is clocked by timer pacer, which is generated by an interval programming ti

Page 33

Operation Theory • 31 4.3 External Clock Mode The digital input is clocked by external strobe, which is from Pin 19 (I_REQ) of CN2 (PCI-7200), Pin 24

Page 34

Getting Service from ADLINK Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you need any help or service, please contact us. ADL

Page 35

32 • Operation Theory O_REQ & O_ACK for Digital Output 1. Digital Output Data is moved from PC memory to FIFO of PCI-7200 by usi

Page 36

Operation Theory • 33 4.5 Timing Characteristic 1. I_REQ as input data strobe (Rising Edge Active) th ≥ 60ns tI ≥ 60ns tCYC ≥ 5 PCI CLK Cycle ts ≥

Page 37 - Operation Theory

34 • Operation Theory 3. I_REQ & I_ACK Handshaking valid dataD10~DI31valid datat1t2t5t4t3IN I_REQIN I_ACK t1 ≥ 0ns t5 ≥ 60ns t3 ≥ 2 PCI CLK Cy

Page 38 - 4.2 Timer Pacer Mode

Operation Theory • 35 5. O_REQ & O_ACK Handshaking OUT_REQt1t3valid dataDO0~Do31t1 19nst3t21 PCI CLK Cycle OUT_ACK5 PCI CLK Cycle valid datat2

Page 40 - Digital Output

C/C++ Libraries • 37 5 C/C++ Libraries This chapter describes the software library for operating the card. Only functions in DOS library and Windows

Page 41 - 4.5 Timing Characteristic

38 • C/C++ Libraries 5.2 Programming Guide 5.2.1 Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software drivers u

Page 42

C/C++ Libraries • 39 5.3 _7200_Initial @ Description A PCI-7200 card is initialized according to the card number. Because the PCI-7200 is PCI bus ar

Page 43

40 • C/C++ Libraries 5.4 _7200_Switch_Card_No @ Description After initializing more than one PCI-7200 card, this function is used to select which car

Page 44

C/C++ Libraries • 41 5.6 _7200_AUX_DI_Channel @ Description Read data from the auxiliary digital input channel of cPCI-7200 card. There are 4 digital

Page 45 - C/C++ Libraries

Table of Contents • i Table of Contents Chapter 1 Introduction...1 1.1 Applications...

Page 46 - 5.2 Programming Guide

42 • C/C++ Libraries 5.8 _7200_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are 4 auxiliary digital outpu

Page 47 - 5.3 _7200_Initial

C/C++ Libraries • 43 5.10 _7200_DI_Channel @ Description This function is used to read data from digital input channels (bit). There are 32 digital i

Page 48 - 5.5 _7200_AUX_DI

44 • C/C++ Libraries 5.12 _7200_DO_Channel @ Description This function is used to write data to digital output channels (bit). There are 32 digital o

Page 49 - 5.7 _7200_AUX_DO

C/C++ Libraries • 45 5.13 _7200_Alloc_DMA_Mem @ Description Contact Windows 95/98 system to allocate a block of contiguous memory for single-buffered

Page 50 - 5.9 _7200_DI

46 • C/C++ Libraries 5.14 _7200_Free_DMA_Mem @ Description Releases system DMA memory. This function is only available in Windows 95/98. @ Syntax Vis

Page 51 - 5.11 _7200_DO

C/C++ Libraries • 47 denotes the actual size of allocated memory for each half of circular buffer. @ Return Code ERR_NoError ERR_SmallerDMAMemAllocat

Page 52 - 5.12 _7200_DO_Channel

48 • C/C++ Libraries Bus Mastering DMA mode of the PCI-7200: PCI bus mastering offers the highest possible speed available on the PCI-7200. When the

Page 53 - 5.13 _7200_Alloc_DMA_Mem

C/C++ Libraries • 49 @ Syntax Visual C++ (Windows 95) int W_7200_DI_DMA_Start (U8 mode, U32 count, U32 handle, Boolean wait_trg, U8 trg_pol, Boolean

Page 54 - 5.15 _7200_Alloc_DBDMA_Mem

50 • C/C++ Libraries clear_fifo: 0: retain the FIFO data 1: clear FIFO data before perform digital input disable_di: 0: digital input oper

Page 55 - 5.17 _7200_DI_DMA_Start

C/C++ Libraries • 51 5.19 _7200_DI_DMA_Stop @ Description This function is used to stop the DMA data transferring. After executing this function,

Page 56

Table of Contents • ii 4.3 External Clock Mode ... 31 4.4 Handshaking ...

Page 57

52 • C/C++ Libraries 5.21 _7200_CheckHalfReady @ Description When you use _7200_DI_DMA_Start to sample digital input data and double buffer mode i

Page 58 - 5.18 _7200_DI_DMA_Status

C/C++ Libraries • 53 5.23 _7200_GetOverrunStatus @ Description When using _7200_DI_DMA_Start to convert Digital I/O data with double buffer mode e

Page 59 - 5.20 _7200_DblBufferMode

54 • C/C++ Libraries C/C++ (DOS) int _7200_DO_DMA_Start (U8 mode, U32 count, U32 *do_buffer, Boolean repeat) @ Argument mode: Digital output trigge

Page 60 - 5.22 _7200_DblBufferTransfer

C/C++ Libraries • 55 C/C++ (DOS) int _7200_DO_DMA_Status (U8 *status , U32 *count) @ Argument status: status of the DMA data transfer. 0: DO_DMA_STOP

Page 61 - 5.24 _7200_DO_DMA_Start

56 • C/C++ Libraries 5.27 _7200_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. There are two conf

Page 62 - 5.25 _7200_DO_DMA_Status

C/C++ Libraries • 57 mode: TIMER_NONCASCADE or TIMER_CASCADE @ Return Code ERR_NoError ERR_InvalidBoardNumber ERR_InvalidTimerMode ERR_BoardNoInit 5.

Page 63 - 5.26 _7200_DO_DMA_Stop

58 • C/C++ Libraries @ Syntax Visual C++ (Windows 95) int W_7200_DO_Timer (U16 c1, U16 c2, Booelan mode) Visual Basic (Windows 95) W_7200_DO_Timer (B

Page 64 - 5.27 _7200_DI_Timer

Double Buffer Mode Principle • 59 6 Double Buffer Mode Principle The data buffer for a double-buffered DMA DI operation is logically a circular buffe

Page 65 - 5.28 _7200_DO_Timer

60 • Double Buffer Mode Principle The PCI-7200 double buffer mode functions were designed according to the principle described above. If using _7200_

Page 66

Limitations • 61 7 Limitations The 12MB/sec data transfer rate can only be possibly achieved in systems where the PCI-7200 card is the only device us

Page 67 - Double Buffer Mode Principle

How to Use This Guide This manual is designed to help users use the PCI-7200, cPCI-7200, and LPCI-7200S. The functionality of PCI-7200, cPCI-7200, a

Page 69 - Limitations

Product Warranty/Service • 63 Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offe

Page 71 - Warranty Policy

Introduction • 1 1 Introduction The PCI-7200, cPCI-7200, and LPCI-7200S are PCI/CompactPCI/Low profile PCI form factor high-speed digital I/O cards,

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